On Periodic Register Need in Software Pipelining

On the Periodic Register Need in Software Pipelining

This article presents several theoretical and funda-mental results on register need in periodic schedules, also knownas MAXLIVE. Our first contribution is a novel formula forcomputing the exact number of registers needed by a scheduledloop. This formula has two advantages: its computation can bedone using a polynomial algorithm with O(n lgn) complexity(n is the number of...

Register-Sensitive Software Pipelining

In this paper, we propose an integrated approach for register-sensitive software pipelining. In this approach, the heuristics proposed in the stage scheduling method of Eichenberger and Davidson [4] are integrated with the iterative scheduling method to obtain schedules with high initiation rate and low register requirements. The performance of our integrated software pipelining method was anal...

Optimal Software Pipelining Under Register Constraints

Integrated Register Allocation and Software Pipelining

Software pipelining is a powerful and efficient scheduling technique for exploiting instruction level parallelism in loops, it results in high performance but it increases the register requirements. Two methods are available to reduce the register requirements: increase the schedule length or insert spill code. Traditionally instruction scheduling and register allocation are applied in separate...

Register Assignment for Software Pipelining with Partitioned Register Banks

Many techniques for increasing the amount of instruction-level parallelism (ILP) put increased pressure on the registers inside a CPU. These techniques allow for more operations to occur simultaneously at the cost of requiring more registers to hold the operands and results of those operations, and importantly, more ports on the register banks to allow for concurrent access to the data. One app...